The present invention relates generally to packaging for integrated circuit devices. More particularly, it relates to forming substrates that facilitate testing integrated circuits mounted thereon in strip or panel form.
In the semiconductor industry, there are ongoing efforts to provide smaller, less expensive and faster integrated circuit devices. One aspect of these efforts is directed at the development of more efficient packaging structures, arrangements and processes. One common packaging arrangement is known as grid array based packaging (e.g., ball grid arrays, pin grid arrays, etc.). In a grid array type package, a die is typically mounted on the top surface of a substrate that has an array of contacts on its bottom surface. The die is then electrically connected to landings on the top surface of the substrate. The substrate provides electrical routing and connectivity between the landings on the top surface of the substrate and the contacts on the bottom surface.
Typically, during packaging, substrate strips or panels are provided that have a plurality of distinct molding areas. For lack of the availability of a common term, the molding areas are referred to as tiles herein. The tiles are typically (although not always) separated by thermal expansion slots. A representative substrate strip 101 is illustrated in FIG. 1. Traditionally, a single die was mounted in a die attach area 103 near the center of each tile 102. The die is then electrically coupled to landings 105 on the top surface of the tile 102. The die may be electrically coupled to the landings by a variety of traditional techniques, although wire bonding is most common. The landings 105 are coupled to associated vias 107 by traces 109 on the top surface of tile 102. The vias 107 are electrically conductive and pass through substrate. The vias are then typically coupled to associated contacts (not shown) on the bottom surface of the substrate by traces (not shown) on the bottom surface of the substrate.
After the dice on a particular strip have all been mounted and electrically connected, a plastic cap is typically formed over each die. The packaged integrated circuits are then typically trimmed (i.e. the excess portions of the strip are trimmed away thereby separating the packed integrated circuits from one another). Thereafter, the packaged integrated circuits are typically tested.
As die and package sizes have been reduced, there have been recent efforts to mount a plurality of dice within each tile (molding area) with the intention and result of forming several distinct integrated circuit packages on each substrate tile. Although this approach has many advantages, due to the nature of the way that the substrate strips are formed, the packages cannot be tested in the strip form. Rather, the packaged devices are singulated and then tested in the singulated form.
Although the existing substrate arrangements and individual testing have worked well in the past, as smaller and higher density packaging becomes more common, improved substrate strip structures and improved testing techniques that are less expensive and have less problems than the current structures and techniques will become necessary and desirable.